SN74LS75

The SN74LS75 is designed as 4-bit D latch which is used as temporary storage for binary information between processing units and input/ output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go high.

Some DC characteristics of SN74LS75 have been concluded into several points as follow. (1)Its input high voltage would be min 2.0V with conditions of guaranteed input high voltage for all inputs. (2)Its input low voltage would be max 0.8V with conditions of guaranteed input low voltage for all inputs. (3)Its input clamp diode voltage would be typ -0.65V and max -1.5V with condition of Vcc=min, Iin=-18mA. (4)Its output high voltage would be min 2.7V and typ 3.5V. (5)Its output low voltage would be typ 0.25V and max 0.4V with condition of Iol=4.0mA and would be typ 0.35V and max 0.5V with condition of Iol=8mA. (6)Its input high current would be max 20uA for D input with condition of Vcc=max and Vin=2.7V and it would be max 0.1mA for D input with condition of Vcc=max and Vin=7.0V. (7)Its input low current would be max -0.4mA for D input. (8)Its short circuit current would be min -20mA and max -100mA with condition of Vcc=max. (9)Its power supply current would be max 12mA with condition of Vcc=max.

And some AC characteristics of SN74LS75 are concluded into several points as follow. (1)Its propagation delay, data to Q would be typ 15ns and max 27ns. (2)Its propagation delay, data to -Q would be typ 12ns and max 20ns. (3)Its propagation delay, enable to Q would be typ 15ns and max 27ns. (4)Its propagation delay, enable to -Q would be typ 16ns and max 30ns. And so on. If you have any question or suggestion or want to know more information please contact us for details. Thank you!