SN74LV164A

Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 7 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Voltage range applied to any output in the high-impedance
  or power-off state, V_O(see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 7 V
Output voltage range applied in the high or low state, V_O(see Notes 1 and 2)  . . . . . 
                                                          . . . . . . . . . . . . . . . . . . . . .-0.5 V to V_CC+ 0.5 V 
Input clamp current, I_IK (V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20 mA
Output clamp current, I_OK(V_O < 0)   . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .-50 mA
Continuous output current, I_O(V_O = 0 to V_CC)  . . . . . . . . . . . . . . . . . .. . . . . .±25 mA
Continuous current through V_CC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA
Package thermal impedance, JA(see Note 3):  D package. .. . . . . . . . . . . . .  86/W
                                                                          DB package. .. . . . . .. . . . . . .  96/W
                                                                          DGV package  . . . . . .  . . . . . 127/W
                                                                          NS package  . . . . .  . . . . . . .  76/W
                                                                          PW package  . . . . . . . . . . . . 113/W
                                                                          RGY package   . . . . . . . .. . . . .47/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .-65 to 150


Description

The 'LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V V_CC operation.

These devices LV164A feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input.