SN74LV174A

Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 7 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Output voltage range applied in the high or low state, V_O(see Notes 1 and 2)  . . . . . 
                                                          . . . . . . . . . . . . . . . . . . . . .-0.5 V to V_CC+ 0.5 V 
Input clamp current, I_IK (V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20 mA
Output clamp current, I_OK (V_O< 0 or V _O > V _CC) . . . . . . . . . . . . . . .  . . . . . . ±50 mA
Continuous output current, I_O(V_O = 0 to V_CC)  . . . . . . . . . . . . . . . . . .. . . . . .±25 mA
Continuous current through V_CC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA
Package thermal impedance,  JA (see Note 3):  D package. .. . . . . . . . . . . . . 113/W
                                                                          DB package. .. . . . . .. . . . . . . 131/W
                                                                          DGV package  . . . . . .  . . . . . .180/W
                                                                          NS package  . . . . .  . . . . . . .  111/W
                                                                          PW package  . . . . . . . . . . . . .149/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .-65 to 150


Description

The 'LV174A devices are hex D-type flip-flops designed for 2-V to 5.5-V V_CC operation.

These devices LV174A  are monolithic positive-edge- triggered flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of the clock pulse. When the clock (CLR) input is at either the high or low level, the D-input signal has no effect at the output.