SN74LV174AD

Mounting Style : SMD/SMT
Supply Voltage - Max : 5.5 V
Polarity : Non-Inverting
Input Type : Single-Ended
Output Type : Single-Ended
Maximum Operating Temperature : + 85 C
Packaging : Tube
Logic Family : 74LV
Logic Type : D-Type Flip-Flop
Package / Case : SOIC-16
Number of Circuits : 7
Low Level Output Current : 12 mA
High Level Output Current : - 12 mA
Propagation Delay Time : 20.6 ns


Features:

2-V to 5.5-V VCC Operation
Max tpd of 8.5 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25
Support Mixed-Mode Voltage Operation on All Ports
Latch-Up Performance Exceeds 250 mA Per JESD 17
 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)


Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I_O (V_O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These  re stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated  nder "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7

Description

The 'LV174A devices are hex D-type flip-flops designed for 2-V to 5.5-V V_CC operation. These devices are positive-edge-triggered flip-flops with a direct clear (CLR) input.

LV174A Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of the clock pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.