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SN74LV32A
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MFG:TEXAS Package Cooled:98 D/C:TSSOP

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Part Number: SN74LV32A

MFG: TEXAS

Package Cooled: 98

D/C: TSSOP

Description: These quadruple 2-input positive-OR gates are designed for 2-V to 5.5-V VCC operation.The 'LV32A dev...

SN74LV32A General Description

These quadruple 2-input positive-OR gates are designed for 2-V to 5.5-V V_CC operation.

The 'LV32A devices perform the Boolean function Y = AB or Y = A • B in positive logic.

SN74LV32A Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . −0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. −0.5 V to 7 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 86°C/W
                                                    (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 96°C/W
                                                    (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
                                                    (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
                                                    (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
                                                    (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 47°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
             2. This value is limited to 5.5 V maximum.
             3. The package thermal impedance is calculated in accordance with JESD 51-7.
             4. The package thermal impedance is calculated in accordance with JESD 51-5.

SN74LV32A Features

2-V to 5.5-V V_CC Operation
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical VOHV (Output VOH Undershoot) >2.3 V at V_CC = 3.3 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on All Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
    − 2000-V Human-Body Model (A114-A)
    − 200-V Machine Model (A115-A)
    − 1000-V Charged-Device Model (C101)

SN74LV32A Connection Diagram

SN74LV32A datasheet

SN74LV32A
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Datasheet: SN74LV32A
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