Latches Tri-St Octal D-Type
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
| Number of Circuits : | 8 | Logic Type : | D-Type Transparent Latch | ||
| Logic Family : | LV | Polarity : | Non-Inverting | ||
| Number of Output Lines : | 8 | High Level Output Current : | - 16 mA | ||
| Low Level Output Current : | 32 mA | Propagation Delay Time : | 18 ns at 2.5 V, 14.9 ns at 3.3 V, 9.2 ns at 5 V | ||
| Supply Voltage - Max : | 5.5 V | Supply Voltage - Min : | 2 V | ||
| Maximum Operating Temperature : | + 85 C | Minimum Operating Temperature : | - 40 C | ||
| Package / Case : | SOIC-20 | Packaging : | Tube |
The SN74LV373ADWE4 is one member of the SN74LV373A series.While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
Features of the SN74LV373ADWE4 are:(1)2-V to 5.5-V VCC operation; (2)Max tpd of 8.5 ns at 5 V; (3)support mixed-mode voltage operation on all ports; (4)Ioff Supports partial-power-down mode operation; (5)latch-up performance exceeds 250 mA per JESD 17.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.These devices are fully specified for partial-power-down applications using Ioff.The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The absolute maximum ratings of the SN74LV373ADWE4 can be summarized as:(1)supply voltage range:-0.5 to 7.0V;(2)input voltage range:-0.5 to 7.0V;(3)output voltage range:-0.5 to Vcc+0.5V;(4)input clamp current:-20mA; (5)output clamp current:-50mA; (6)voltage range applied to any output in the high-impedance or power-off state:-0.5 to 7.0V; (7)storage temperature range:-65 to 150.Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
| Technical/Catalog Information | SN74LV373ADWE4 |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Logic Type | D-Type Transparent Latch |
| Independent Circuits | 1 |
| Circuit | 8:8 |
| Output Type | Tri-State |
| Current - Output High, Low | 16mA, 16mA |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (7.5mm Width) |
| Packaging | Tube |
| Operating Temperature | -40°C ~ 85°C |
| Delay Time - Propagation | 1ns |
| Voltage - Supply | 2 V ~ 5.5 V |
| Drawing Number | 296; 4040000-4; DW; 20 |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | SN74LV373ADWE4 SN74LV373ADWE4 |