SN74LV74A

Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 7 V
Input voltage range, V_I (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Voltage range applied to any output in the high-impedance
  or power-off state, V_O(see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V
Output voltage range applied in the high or low state, V_O(see Notes 1 and 2)  . . . . . 
                                                          . . . . . . . . . . . . . . . . . . . . .-0.5 V to V_CC+ 0.5 V 
Input clamp current, I_IK (V_I< 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20 mA
Output clamp current, I_OK(V_O < 0)   . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .-50 mA
Continuous output current, I_O(V_O = 0 to V_CC)  . . . . . . . . . . . . . . . . . .. . . . . .±35 mA
Continuous current through V_CC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±70 mA
Package thermal impedance, JA(see Note 3):  D package. .. . . . . . . . . . . . .  70/W
                                                                          DB package. .. . . . . .. . . . . . .  92/W
                                                                          DGV package  . . . . . .  . . . . . . 58/W
                                                                          NS package  . . . . .  . . . . . . .  78/W
                                                                          PW package  . . . . . . . . . . . . . 60/W
                                                                          PW package  . . . . .. . . . . . . . .83/W
                                                                          RGY package  . . . . . . . . .. . . . .37/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .-65 to 150


Description

These dual positive-edge-triggered D-type flip-flops SN74LV74A are designed for 2-V to 5.5-V V_CC operation.

SN74LV74A A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.