SN74LVC02A

Features:

 EPIC ^TM (Enhanced-Performance Implanted CMOS) Submicron Process
 Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
 Typical V_OHV (Output VOH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
 Inputs Accept Voltages to 5.5 V
 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
 Latch-Up Performance Exceeds 250 mA Per JESD 17
 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W), Chip Carriers
   (FK), and DIPs (J)


Pinout




Specifications

Supply-voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 6.5 V
Input-voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to 6.5 V
Output-voltage range, V_O (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . ....0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, ^qJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
                                                                          DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
                                                                          PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .170°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 65°C to 150°C
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
             2. The value of VCC is provided in the recommended operating conditions table.
             3. The package thermal impedance is calculated in accordance with JESD 51.


Description

The SN54LVC02A quadruple 2-input positive- NOR gate is designed for 2.7-V to 3.6-V V_CC operation and the SN74LVC02A quadruple 2-input positive-NOR gate is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC02A devices perform the Boolean function Y = A + B or Y = A • B in positive logic.

SN74LVC02A Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

The SN54LVC02A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LVC02A is characterized for operation from 40°C to 85°C.