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SN74LVC112A

Features: ` Operates From 1.65 V to 3.6 V` Inputs Accept Voltages to 5.5 V` Max tpd of 4.8 ns at 3.3 V` Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C` Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C` Latch-Up Performance Exceeds 250 mA Per JESD 17` ...

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SN74LVC112A: Features: ` Operates From 1.65 V to 3.6 V` Inputs Accept Voltages to 5.5 V` Max tpd of 4.8 ns at 3.3 V` Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C` Typical VOHV (Output ...

SN74LVC112A Data Sheet

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Part Number:
SN74LVC112A
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` Operates From 1.65 V to 3.6 V
` Inputs Accept Voltages to 5.5 V
` Max tpd of 4.8 ns at 3.3 V
` Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
` Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
` Latch-Up Performance Exceeds 250 mA Per JESD 17
` ESD Protection Exceeds JESD 22
   2000-V Human-Body Model (A114-A)
   200-V Machine Model (A115-A)
   1000-V Charged-Device Model (C101)


Pinout

Connection Diagram


Specifications

  MIN MAX UNIT
VCC Supply voltage range 0.5 6.5 V
VI Input voltage range(2) 0.5 6.5 V
VO Output voltage range(2) (3) 0.5 VCC + 0.5 V
IIK Input clamp current VI < 0   50 mA
IOK Output clamp current VO < 0   50 mA
IO Continuous output current   ±50 mA
Continuous current through VCC or GND   ±100 mA
 JA Package thermal impedance D package   73 °C/W
DB package   82
DGV package   120
NS package   64
PW package   108
Tstg Storage temperature range 65 150 °C



Description

This dual negative-edge-triggered J-K flip-flop SN74LVC112A is designed for 1.65-V to 3.6-V VCC operation.

A low level at the preset (PRE ) or clear (CLR ) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can perform as a toggle flip-flop by tying J and K high.

SN74LVC112A Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.




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