Features: EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Ioff Feature Supports Partial-Power-Down Mode Operation Supports 5-V VCC Operation Package Options Include Plastic Small-Outline Transistor (DBV, DCK) PackagesPinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . ...
SN74LVC1G125: Features: EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Ioff Feature Supports Partial-Power-Down Mode Operation Supports 5-V VCC Operation Package Options Include Plastic Small-Outl...
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Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . .. .. . . . . . . . . . . . 0.5 V to 6.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . .. . .. . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . .......... . . . . . . . . . . . 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . .. . . . .. . . . . . . ±100 mA
Package thermal impedance, JA (see Note 3): DBV package . . . .. . . . . . . 347°C/W
DCK package . . . . . . .. . . . 389°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . ... . . 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
This bus buffer gate SN74LVC1G125 is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G125 features a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, SN74LVC1G125 OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device SN74LVC1G125 is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G125 is characterized for operation from 40°C to 85°C.