SN74LVC2952A

Features:

 EPIC E  ^TM (Enhanced-Performance Implanted CMOS) Submicron Process
 Typical VOLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
 Typical VOHV (Output VOH Undershoot)> 2 V at V_CC = 3.3 V, T_A = 25°C
 Power Off Disables Outputs, Permitting Live Insertion
 Supports Mixed-Mode Signal Operation onAll Ports (5-V Input/Output Voltage With 3.3-V VCC)
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V  Using Machine Model (C = 200 pF, R = 0)
 Latch-Up Performance Exceeds 250 mA Per JESD 17
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages


Pinout




Specifications

Supply voltage range, V_^CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 0.5 V to 6.5 V
Input voltage range, V_I: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, V_O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V_O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . ±100 mA
Package thermal impedance, q_JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . 104°C/W
                                                                          DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . . 81°C/W
                                                                          PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . 120°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
             2. The value of VCC is provided in the recommended oprating conditions table.
             3. The package thermal impedance is calculated in accordance with JESD 51.


Description

This SN74LVC2952A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC2952A consists of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.

SN74LVC2952A Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC2952A is characterized for operation from 40°C to 85°C.