Features: `Member of the Texas Instruments Widebus+™ Family Operation
`Ioff Supports Partial-Power-Down Mode
`Operates From 1.65 V to 3.6 V
`Supports Mixed-Mode Signal Operation (5-VInput and Output Voltages With 3.3-V VCC)
`Inputs Accept Voltages to 5.5 V
`Max tpd of 4.2 ns at 3.3 V
`Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
`Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25
`ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model (C101)
`Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25
Specifications
| |
MIN |
MAX |
UNIT |
| VCC |
Supply voltage range |
0.5 |
6.5 |
V |
| VI |
Input voltage range(2) |
0.5 |
6.5 |
V |
| VO |
Voltage range applied to any output in the high-impedance or power-off state(2) |
0.5 |
6.5 |
V |
| VO |
Voltage range applied to any output in the high or low state(2) (3) |
0.5 |
VCC + 0.5 |
V |
| IIK |
Input clamp current |
VI < 0 |
50 |
mA |
| IOK |
Output clamp current |
VO < 0 |
50 |
mA |
| IO |
Continuous output current |
±50 |
mA |
| |
Continuous current through each VCC or GND |
±100 |
mA |
| JA |
Package thermal impedance(4) |
GKE/ZKEpackage |
|
40 |
/W |
| Tstg |
Storage temperature range |
65 |
150 |
|
DescriptionThis 32-bit transparent D-type latch SN74LVC32373A is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
SN74LVC32373A A buffered output-enable (OE ) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
SN74LVC32373AOE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
SN74LVC32373A Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
This device SN74LVC32373A is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, SN74LVC32373A OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
SN74LVC32373A Data Sheet
