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SN74LVC374

Features: • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C• Package Options Include Plastic Small-Outline (DW),...

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SeekIC No. : 004499329 Detail

SN74LVC374: Features: • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C• Typical VOHV (Output VOH Under...

SN74LVC374 Data Sheet

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Part Number:
SN74LVC374
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI . . . . . . . . . .  . . . . . . . . . . . .. . . .  . . . . .. . . . . . . . . . .  . . . . .0.5 V to 4.6 V
Output voltage range, VO (see Notes 1) . . . . .  . . . . . . . . . . . . . . . . . . . .  . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through VCC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ±100mA
Maximum power package dissipation at TA = 55°C (in still air)(see Note 2):DB package  . .  . . 0.6 W
                                                                                                                     DW package  . . . . 1.6 W
                                                                                                                     PW package  . . . . .0.7 W
Operating free-air temperature range, TA  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .40°C to 85°C 
Storage temperature range  . . .  . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .  . . 65°C to 150°C  


Description

This octal edge-triggered D-type flip-flop SN74LVC374 is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVC374 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

On the positive transition of the SN74LVC374 clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

SN74LVC374 A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74LVC374 is characterized for operation from 40°C to 85°C.




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