Features: • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C• Package Options Include Plastic Small-Outline (DW),...
SN74LVC574: Features: • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C• Typical VOHV (Output VOH Under...
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This octal edge-triggered D-type flip-flop SN74LVC574 is designed for 2.7-V to 3.6-V VCC operation.
The SN74LVC574 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
SN74LVC574 A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The SN74LVC574 output-enable (OE) input does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN74LVC574 is characterized for operation from 40°C to 85°C.