SN74LVC821A

Features:

EPIC^tm (Enhanced-Performance Implanted CMOS) Submicron Process
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
Power Off Disables Outputs, Permitting Live Insertion
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Latch-Up Performance Exceeds 250 mA Per JESD 17
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline DB), and Thin Shrink Small-Outline (PW) Packages


Specifications

Supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V
Input voltage range, VI (see Note 1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .  . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, IOK (VO < 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous output current, IO   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ±100 mA
Package thermal impedance, JA (see Note 3): DB package   . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .  . . . . . 104°C/W
DW package   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . 81°C/W
PW package   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .  . . . . . 120°C/W
Storage temperature range,    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .. . . . 65°C to 150°C


Description

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.The SN74LVC821A is characterized for operation from 40°C to 85°C.