SN74LVCH16245A Selling Leads, Price trend, SN74LVCH16245A DataSheet download, circuit diagram from SeekIC.com

Features: * Member of the Texas Instruments WidebusE Family* EPICE (Enhanced-Performance Implanted CMOS) Submicron Process* Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25* Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25* Supports Mixed-Mode Signal Oper...

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SeekIC No. : 004499388 Detail

SN74LVCH16245A: Features: * Member of the Texas Instruments WidebusE Family* EPICE (Enhanced-Performance Implanted CMOS) Submicron Process* Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25* Ty...

SN74LVCH16245A Data Sheet

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Part Number:: SN74LVCH16245A
Supply Ability:: 5000

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Product Details

Description

Features:

* Member of the Texas Instruments
   WidebusE Family
* EPICE (Enhanced-Performance Implanted
   CMOS) Submicron Process
* Typical V_OLP (Output Ground Bounce)
   < 0.8 V at V_CC = 3.3 V, T_A = 25
* Typical V_OHV (Output VOH Undershoot)
   > 2 V at V_CC = 3.3 V, T_A = 25
* Supports Mixed-Mode Signal Operation on
   All Ports (5-V Input/Output Voltage With
   3.3-V V_CC)
* Power Off Disables Inputs/Outputs,
   Permitting Live Insertion
* ESD Protection Exceeds 2000 V Per
   MIL-STD-883, Method 3015; Exceeds 200 V
   Using Machine Model (C = 200 pF, R = 0)
* Latch-Up Performance Exceeds 250 mA Per
   JESD 17
* Bus Hold on Data Inputs Eliminates the
   Need for External Pullup/Pulldown
   Resistors
* Package Options Include Plastic 300-mil
   Shrink Small-Outline (DL) and Thin Shrink
   Small-Outline (DGG) Packages

Pinout

Connection Diagram

Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . .-0.5 V to 6.5 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, V_O
   (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .-0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V_O
   (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . .-50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .-50 mA
Continuous output current, I_O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through each V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... . . . . . . .±100 mA
Package thermal impedance, _JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . .......... . . . . . . .70/W
                                                                          DGV package . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . . .58/W
                                                                          DL package . . . . . . . . . . . . . . . . . . . . . . . ..... . . . . . . . .63/W
                                                                          GQL/ZQL package . . . . . . . . . . . . . . . . . . ....... . . . . . . .42/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. .. . . .?65 to 150

Description

This 16-bit (dual-octal) noninverting bus transceiver SN74LVCH16245A is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH16245A is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

This device SN74LVCH16245A can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (<a href="#" style="text-decoration:overline;">OE</a>) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, <a href="#" style="text-decoration:overline;">OE</a> should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74LVCH16245A Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74LVCH16245A is characterized for operation from 40 to 85.

SN74LVCH16245A

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