SN74LVCH16646A

Member of the Texas Instruments
    Widebus™ Family
EPIC ™(Enhanced-Performance Implanted
    CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
    < 0.8 V at V_CC= 3.3 V, T_A = 25°C
Typical VOHV (Output VOH Undershoot)
    > 2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation on
    All Ports (5-V Input/Output Voltage With
    3.3-V V_CC)
Power Off Disables Outputs, Permitting
    Live Insertion
ESD Protection Exceeds 2000 V Per
    MIL-STD-883, Method 3015; Exceeds 200 V
    Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
    JESD 17
Bus Hold on Data Inputs Eliminates the
    Need for External Pullup/Pulldown
    Resistors
Package Options Include Plastic 300-mil
    Shrink Small-Outline (DL) and Thin Shrink
    Small-Outline (DGG) Packages

This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V V_CC operation.The SN74LVCH16646A can be used as two 8-bit
transceivers or one 16-bit transceiver. The device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.

Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVCH16646A.

SN74LVCH16646A Output-enable (OE ) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE  is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.