SN74LVT8980

The SN74LVT8980 embedded test-bus controllers (eTBC) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBC is not a boundary-scannable device; rather, SN74LVT8980's function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBC enables the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels.

The eTBC masters all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST). All such signals can be connected directly to the associated target IEEE Std 1149.1 devices SN74LVT8980 without need for additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK cycles; the eTBC automatically handles all associated serial-data justification.

Conceptually, the eTBC operates as a simple 8-bit memory- or I/O- mapped peripheral to a microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBC via SN74LVT8980's generic host interface, which includes an 8-bit data bus (D7D0) and a 3-bit address bus (A2A0). Read/write select (R/W) and strobe (STRB) signals are implemented so that the critical host-interface timing is independent of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into, a host read/write cycle when the eTBC cannot respond immediately to the requested read/write operation. High-level commands are issued by the host to cause the eTBC to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A 32-bit counter of SN74LVT8980 can be programmed to allow a predetermined number of scan or execute cycles.

About SN74LVT8980,During scan operations, serial data that appears at the TDI input is transferred into a serial-to-4 * 8-bit-parallel first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to eight bits at a time, to a 4 * 8-bit-parallel-to-serial FIFO write buffer.

In addition to such simple state-movement, scan, and run-test operations, the eTBC SN74LVT8980 supports several additional commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored bac to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TI's addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller host to monitor the TDO or TMS data streams output by the eTBC.

The eTBC SN74LVT8980's flexible clocking architecture allows the user to choose between free-running (in which the TCK always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move, run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode is also available in which the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host. These features ensure that virtually any IEEE Std 1149.1 target device or device chain even where such may not fully comply to IEEE Std 1149.1 can be serviced by the eTBC SN74LVT8980.

While most operations of the eTBC SN74LVT8980 are synchronous to CLKIN, a test-output enable (TOE) is provided for output control of the TAP outputs, and a reset (RST) input is provided for hardware reset of the eTBC. The former can be used to disable the eTBC so that an external controller can master the associated IEEE Std 1149.1 test bus. The SN54LVT8980 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74LVT8980 is characterized for operation from 40°C to 85°C.