SN74LVTH16835

· Members of the Texas Instruments Widebus^TM Family
· State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
· Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
· Support Unregulated Battery Operation Down to 2.7 V
· Typical VOLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
· Ioff and Power-Up 3-State Support Hot Insertion
· Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
· Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
· Flow-Through Architecture Optimizes PCB Layout
· Latch-Up Performance Exceeds 500 mA Per JESD 17
· ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
· Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high-impedance
   or power-off state, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high state, V_O (see Note 1) . . . . . 0.5 V to V_CC + 0.5 V
Current into any output in the low state, I_O: SN54LVTH16835 . . . . . . . . . . . . .  . . .. .. .. . . . . . 96 mA
                                                                       SN74LVTH16835 . . . . . . . . . . . . . . .. .. .. .. . . . . 128 mA
Current into any output in the high state, I_O (see Note 2): SN54LVTH16835 . . . . . . .. .. .. .. . . 48 mA
                                                                                             SN74LVTH16835 . . . . . . .. .. .. .. . . 64 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. . . . . 50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .. .. .. .. . 50 mA
Package thermal impedance, _JA (see Note 3): DGG package . . . . . . . . . . . . . . . . .. .. .. .. . . 81°C/W
                                                                          DL package . . . . . . . . . . . . . . . .. .. .. .. . . . . . 74°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . .. . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V_O > V_CC.
3. The package thermal impedance is calculated in accordance with JESD 51.

The SN74LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

About SN74LVTH16835,Data flow from A to Y is controlled by the output-enable (OE) input. These devices operate in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE is high, the outputs are in the high-impedance state.

Active bus-hold circuitry is provided by SN74LVTH16835 to hold unused or floating data inputs at a valid logic level.

When V_CC is between 0 and 1.5 V, the devices SN74LVTH16835 are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.