SN74LVTH646

 · State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
 · I_off and Power-Up 3-State Support Hot Insertion
 · Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
 · Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
 · Support Unregulated Battery Operation Down to 2.7 V
 · Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
 · Latch-Up Performance Exceeds 500 mA Per JESD 17
 · ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
 · Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (JT) DIPs

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, V_O (see Note 1). . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high state, V_O (see Note 1) . .. . . 0.5 V to V_CC + 0.5 V
Current into any output in the low state, I_O: SN54LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I_O (see Note 2): SN54LVTH652 . . . . . . . . . . . . . . . . 48 mA
SN74LVTH652 . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, _JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
DGV package . . . . . . . . . . . . . .. . . . . . . . . . 139°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . .. . . . . . . . . . . 65°C to 150°

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the utput is in the high state and V_O > V_CC. 3. The package thermal impedance is calculated in accordance with JESD 51

These bus transceivers and registers SN74LVTH646 are designed specifically for low-voltage (3.3-V) V _CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The SN74LVTH646 devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'LVTH646.

Output-enable (OE) and direction-control (DIR) inputs are provided by SN74LVTH646 to control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both.
 
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) of SN74LVTH646 determines which bus receives data whenOE is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.