SN74SSQEA32882

The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs,DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the"QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.

Features of the SN74SSQEA32882 are:(1)JEDEC SSTE32882 Compliant; (2)1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs; (3)CKE Powerdown Mode for Optimized System Power Consumption; (4)1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Differential Outputs; (5)1.5V/1.35V CMOS Inputs; (6)Checks Parity on Command and Address (CS-Gated) Data Inputs; (7)Configurable Driver Strength; (8)Uses Internal Feedback Loop.

The absolute maximum ratings of the SN74SSQEA32882 can be summarized as:(1)Supply voltage 0.4 to +1.975 V; (2)Receiver input voltage See (2)and (3) 0.4 to VDD + 0.5 V; (3)Reference voltage 0.4 to VDD + 0.5 V; (4)Driver output voltage See (2) and (3)0.4 to VDD + 0.5 V; (5)Input clamp current VI < 0 or VI > VDD 50 mA; (6)Output clamp current VO < 0 or VO > VDD ±50 mA; (7)Continuous output current 0 < VO < VDD ±50 mA; (8)Continuous current through each VDD or GND pin ±100 mA; (9)Storage temperature 65 to +150 °C.

If you want to know more information such as the electrical characteristics of SN74SSQEA32882 ,please download the datasheet in www.seekdatasheet.com .