PinoutSpecificationsSupply voltage range, VCCor VDDQ. . . . . . . . . . . . . . . . . . .0.5 V to 4.6 VInput voltage range, VI(see Note 1). . . . . . . . . . .. . 0.5 V to VCC+ 0.5 VOutput voltage range, VO(see Notes 1 and 2) . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VI< 0) . . . . . ....
SN74SSTL16837A: PinoutSpecificationsSupply voltage range, VCCor VDDQ. . . . . . . . . . . . . . . . . . .0.5 V to 4.6 VInput voltage range, VI(see Note 1). . . . . . . . . . .. . 0.5 V to VCC+ 0.5 VOutput voltage r...
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This 20-bit universal bus driver SN74SSTL16837A is designed for 3-V to 3.6-V VCC operation and SSTL_3 or LVTTL I/O levels.
Data flow from A to Y is controlled by the output-enable (OE</a>) input. The device SN74SSTL16837A operates in the transparent mode when latch enable (LE) is high. The A data is latched if LE is low and clock (CLK) is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE</a> is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE</a> should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver SN74SSTL16837A.
The SN74SSTL16837A is characterized for operation from 0°C to 70°C.