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SN74SSTL32867

PinoutSpecificationsSupply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .0.5 V to 3.6 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .0.5 V to VCC + 0.5 VOutput voltage range, VO (see...

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SN74SSTL32867: PinoutSpecificationsSupply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .0.5 V to 3.6 VInput voltage range, VI (see Note 1) . . . . . . . ....

SN74SSTL32867 Data Sheet

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Part Number:
SN74SSTL32867
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Pinout

Connection Diagram


Specifications

Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Input voltage range, VI (see Note 1)  . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2)  . . . . . . . . . . . . . . .  . . . . . . . . .0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .50 mA
Output clamp current, IOK (VO < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Continuous output current, IO (VO = 0 to VDDQ)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through each VCC, VDDQ, or GND  . . . . . . . . . . . . .  . . . . . . .  . . . . . . . . . .±100 mA
Package thermal impedance, JA (see Note 3)  . . . . . . . . . . . . . . . . . . .. . . . . . .  . . . . . . . . . . . .40°C/W
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C


Description

This 26-bit registered buffer SN74SSTL32867 is designed for 2.3-V to 2.7-V VCC operation and SSTL_2 input and unterminated LVCMOS-output applications.

About SN74SSTL32867, Data flow from A to Y is controlled by differential clock (CLK, CLK) inputs and the LVTTL reset (RESET) input. Data are triggered on the positive edge of the positive clock (CLK). The negative clock (CLK) is used to maintain noise margins. When RESET is low, all registers are reset, and all outputs are low.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

The SN74SSTL32867 is characterized for operation from 0°C to 70°C.




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