SN74SSTU32864

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer SN74SSTU32864 is designed for 1.7-V to 1.9-V V_CC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
. SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.The SN74SSTU32864 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low.

The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration,the A6, D6, and H6 terminals are driven low and should not be used.

The device SN74SSTU32864 supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOSRESET and Cn inputs always must be held at a valid logic high or low level.

About SN74SSTU32864,The two V_REF pins (A3 and T3), are connected together internally by approximately 150 . However, it is necessary to connect only one of the two V_REF pins to the external V_REF power supply. An unused V_REF pin should be erminated with a V_REF coupling capacitor.