SN74SSTU32866GKER

Packaging : Reel
Logic Type : CMOS
Number of Circuits : 1
Logic Family : SSTU
High Level Output Current : - 8 mA
Low Level Output Current : 8 mA
Supply Voltage - Max : 1.9 V
Maximum Operating Temperature : + 70 C
Package / Case : BGA MICROSTAR-96
Maximum Clock Frequency : 500 MHz
Propagation Delay Time : 2.5 ns


Features:

· Member of the Texas Instruments Widebus+ Family
· Pinout Optimizes DDR2 DIMM PCB Layout
· Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
· Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
· Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
· Supports SSTL_18 Data Inputs
· Differential Clock (CLK and CLK CLK) Inputs
· Supports LVCMOS Switching Levels on the Control and RESET) Inputs
· Checks Parity on DIMM-Independent Data Inputs
· Able to Cascade with a Second SN74SSTU32866
· RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low, Except QERR
· Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
· ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)


Specifications

Supply voltage range, V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Input voltage range, V_I (see Notes 1 and 2). . . . . . . . . . . . . . . .  . . . . . . .−0.5 V to 2.5 V
Output voltage range, V_O (see Notes 1 and 2) . . . . . . . . .  . . . . . .−0.5 V to VCC + 0.5 V 
Input clamp current, IIK (V_I < 0 or V_I > V_CC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Output clamp current, IOK (V_O < 0 or V_O > V_CC)  . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous output current, I_O (V_O = 0 to VCC)  . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through each V_CC or GND . . . . . . . . . . . . . . . . . . . .  . . . . . .±100 mA
Package thermal impedance, JA (see Note 3)  . . . . . . . . . . . . . . . . . . . .  . . . . . .36°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . −65°C to 150°C


Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer SN74SSTU32866GKER is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset (RESET RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR ) QERR) output. The SN74SSTU32866 operates from a differential clock (CLK and CLK ) CLK). Data are registered at the crossing of CLK going high and CLK ). going low

. The SN74SSTU32866GKER accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2−D3, D5−D6, D8−D25 when C0 = 0 and C1 = 0; D2−D3, D5−D6, D8−D14 when C0 = 0 and C1=1; or D1−D6, D8−D13 when C0 = 1 and C1=1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.

When SN74SSTU32866GKER used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated. When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high.

The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTU32866GKER.

The QERR output of the first SN74SSTU32866GKER is left floating, and the valid error information is latched on the QERR output of the second SN74SSTU32866. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity-error duration or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS DCS, DODT, and CSR , CSR) are not included in the parity-check computation.

The SN74SSTU32866GKER C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins. In the DDR2 RDIMM application, RESET ) is specified to be completely asynchronous with respect to CLK and CLK CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the SN74SSTU32866GKER data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET . until the input receivers are fully enabled, the design of the SN74SSTU32866GKER ensures that the outputs remain low, thus ensuring there will be no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low, except QERR QERR. The LVCMOS RESET . and Cn inputs always must be held at a valid logic high or low level.

The device SN74SSTU32866GKER also supports low-power active operation by monitoring both system chip select (DCS and CSR CSR) inputs and gates the Qn and PPO outputs from changing states when both DCS ) and CSR inputs are high. If either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1 LPS1) is high (one cycle after DCS ) and CSR go high), the device gates the QERR output from changing states.

If LPS1 is low, the QERR output functions normally. The RESET input has priority over the DCS and CSR control and, when driven low, forces the Qn and PPO outputs low and forces the QERR output high. If the DCS control functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input should be pulled up to VCC through a pullup resistor. The two VREF pins (A3 and T3) are connected together internally by approximately 150 Ω. However, SN74SSTU32866GKER is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.

 

Parameters:

Technical/Catalog Information	SN74SSTU32866GKER
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Logic Type	Configurable Registered Buffer with Address-Parity Test
Mounting Type	Surface Mount
Package / Case	96-LFBGA
Supply Voltage	2.3 V ~ 2.7 V
Packaging	Cut Tape (CT)
Operating Temperature	0°C ~ 70°C
Drawing Number	296; 4188953; GKE; 96
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	SN74SSTU32866GKER SN74SSTU32866GKER 296 18826 1 ND 296188261ND 296-18826-1