SN74SSTVF32852

Features:

 Member of the Texas Instruments Widebus_^TM Family
Operates at 2.3 V to 2.7 V for PC1600,PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
 Pinout and Functionality Compatible With JEDEC Standard SSTV32852
Pinout Optimizes 1U DDR DIMM Layout
600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV32852 in PC2700 DIMM Applications
1-to-2 Outputs Support Stacked DDR DIMMs
One Device Per DIMM Required
Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
Outputs Meet SSTL_2 Class I Specifications
Supports SSTL_2 Data Inputs Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the RESET  Input
RESET  Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
  2000-V Human-Body Model (A114-A)
  200-V Machine Model (A115-A)
  1000-V Charged-Device Model (C101)


Specifications

Supply voltage range, V_CC or V_DDQ . . . . . . . . . . . . . . .  . .  . . .0.5 V to 3.6 V
Input voltage range, V_I (see Notes 1 and 2)  . . . .        .0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Notes 1 and 2) . . . .   . 0.5 V to V_DDQ + 0.5 V
Input clamp current, I_IK (V_I < 0)  . . . . . . . . . . . . . . . . . . . .. . .        . . .50 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_DDQ)  . . . . . . . . .           . .±50 mA
Continuous output current, I_O (V_O = 0 to V_DDQ)  . . . . . . . . . .    .        .±50 mA
Continuous current through each V_CC, V_DDQ, or GND . . . . . . . .         .±100 mA
Package thermal impedance, _JA(see Note 3). . . . . . . . . . ..  .         . . .36°C/W
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . .         ..65°C to 150°C


Description

   This 24-bit to 48-bit registered buffer SN74SSTVF32852 is designed for 2.3-V to 2.7-V V_CC operation.

   All SN74SSTVF32852 inputs are SSTL_2, except the LVCMOS reset (RESET ) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications.

   The SN74SSTVF32852 operates from a differential clock (CLK and CLK ). Data are registered at the crossing of CLK going high andCLK going low.

   The device SN74SSTVF32852 supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, whenRESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level.

   To ensure defined outputs from the SN74SSTVF32852 register before a stable clock has been supplied, RESET must be held in the low state during power up.