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SN75518

PinoutSpecificationsSupply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .15 VSupply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . .70 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . ....

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SeekIC No. : 004499663 Detail

SN75518: PinoutSpecificationsSupply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .15 VSupply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

SN75518 Data Sheet

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Part Number:
SN75518
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Pinout

Connection Diagram


Specifications

Supply voltage, VCC1 (see Note 1)  . . . . . . . . . . . . . . . . . .. . . . . . . . .  . . . . .15 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . .70 V
Input voltage, VI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .VCC1
Continuous total power dissipation . . . . . . . . . . . . . .See Dissipation Rating Table
Operating free-air temperature range, TA:SN65518  . . . . . . . . . .40°C to 85°C
                                                                  SN75518  . . . . . . .  . . . . .0°C to 70°C
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . .  . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds:
N package . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .  . . . . . . .. . . . . . . . 260°C
NOTE 1: Voltage values are with respect to network ground terminal.


Description

The SN65518 and SN75518 are monolithic BIDFET† integrated circuits designed to drive a dot matrix or segmented vacuum fluorescent
display.

Each device SN75518 consists of a 32-bit shift register, 32 latches, and 32 output AND gates. Serial data is entered into the shift register on the low-to-high transition of CLOCK. While LATCH ENABLE is high, parallel data is transferred to the output buffers through a 32-bit latch. Data present in the latch during the high-to-low transition of LATCH ENABLE is latched. When STROBE is low, all Q outputs are enabled. When STROBE is high, all Q outputs are low.

Serial data output from the shift register may be used to cascade additional devices. This output is not affected by LATCH ENABLE or STROBE.

The SN65518 is characterized for operation from 40°C to 85°C. The SN75518 is characterized for operation from 0°C to 70°C.




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