SN75LVDS81

Supply voltage range, V_CC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Output voltage range, V_O (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V_CC + 0.5 V
Input voltage range, V_I (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .. . . see Dissipation Rating Table
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . .  . . . . .260

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.

The SN75LVDS81 FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS81 can also be used in 21-bit links with the SN75LVDS86 receiver.

When SN75LVDS81 transmitting, data bits D0 through D27 are each loaded into registers upon the falling edge of the input clock signal (CLKIN) The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS81 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on SHTDN clears all internal registers to a low level.

The SN75LVDS81 is characterized for operation over free-air temperature ranges of 0C to 70C.