SN75LVDS84A

Pinout




Specifications

Supply voltage range, V_CC(see Note 1) . . . . . . . . . . . . . . . . . . .  . . . . 0.5 V to 4 V
Input and output voltage ranges, V_I , V_O (all terminals) . . . . .0.5 V to V_CC + 0.5 V 
Continuous total power dissipation . . . . . . . . . . . . . . .  See Dissipation Rating Table
Electrostatic discharge: ESD machine model . . . . . . . . . . . . . . . . . . . . . . . . .. . 200 V
ESD human-body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6000 V
ESD charged-device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . .  260 


Description

The SN75LVDS84A FlatLink transmitter contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0 D20 are each loaded into registers of the SN75LVDS84A upon the falling edge.The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.