SN75LVDS86ADGG

Logic Family :
Number of Receivers :
Receiver Signal Type :
Interface Type :
Operating Supply Voltage : 3.3 V
Packaging : Tube
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Package / Case : TSSOP-48


Features:

  3:21 Data Channel Expansion at up to
     163 Million Bytes per Second Throughput
  Suited for SVGA, XGA, or SXGA Display
     Data Transmission From Controller to
     Display With Very Low EMI
  3 Data Channels and Clock Low-Voltage
  Differential Channels In and 21 Data and
     Clock Low-Voltage TTL Channels Out
  Operates From a Single 3.3-V Supply
  Tolerates 4-kV HBM ESD
  Packaged in Thin Shrink Small-Outline
     Package (TSSOP) With 20-Mil Terminal
     Pitch
  Consumes Less Than 1 mW When Disabled
  Wide Phase-Lock Input Frequency Range
     31 MHz to 68 MHz
  No External Components Required for PLL
  Inputs Meet or Exceed the Standard
     Requirements of ANSI EIA/TIA-644
     Standard
  Improved Replacement for the DS90C364
     and SN75LVDS86
  Improved Jitter Tolerance


Pinout




Specifications

Supply voltage range, V_CC (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4 V

Voltage range at any terminal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 0.5 V to VCC + 0.5 V
Electrostatic discharge (see Note 2):All pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . .4 KV
                                                         All pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   200 V

Continuous total power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Dissipation Rating Table

Storage temperature range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 260 


Description

The SN75LVDS86ADGG FlatLink receiver contains three serial-in 7-bit parallel-out shift registers and four low-voltage differential signaling (LVDS) line
receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84,or '85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The SN75LVDS86ADGG presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS86ADGG requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN  ) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low level on this signal clears all internal registers to a low level.

The SN75LVDS86ADGG is characterized for operation over ambient free-air temperatures of 0 to 70.

Parameters:

Technical/Catalog Information	SN75LVDS86ADGG
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Number of Drivers/Receivers	0/4
Type	Receiver
Voltage - Supply	3 V ~ 3.6 V
Package / Case	48-TSSOP
Packaging	Tube
Protocol	RS644
Drawing Number	296; 4040078; DGG; 48, 56, 64
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN75LVDS86ADGG SN75LVDS86ADGG 296 1998 5 ND 29619985ND 296-1998-5