SP1204

The organization and complexity of the SP1204 array makes it ideally suited for integrating complete analog system functions on a single silicon chip. The SP1204 employs a tile based architecture where each tile has been configured (sized) so that it can contain a complete analog function. Pre-defined macro functions which fit these tiles are available and can be used to iplement analog systems thus eliminating the tedious task of transistor level desi n. Using this approach also reduces bath the manpower and elapsed time required to complete a design. while increasing the probability of first time success.

Each tile on the SP1204 consists of 12 SNPN & 12 SPNP transistors arranged in a 3 x 8 matrix. There are both A type & 5 type tiles. The only difference between the two tile types is that the lcations of the SNPN & SPNP transistors in the middle row of the tile are reversed. As a result, A type tiles have two NPN Quads & one PNP Quad while the type tiles have two PNP Quads and one NPN Quad. This feature simplifies many types of layouts. The SPl204 is organized as a 4 x 4 matrix of tiles. The top and bottom rows have A type tiles while the two middle rows contain the type tiles. Sixteen P-JFETs, arranged in quads, lie across the center of the die. The P-JFETs are only available with the 35 Volt process. (These areas are inactive when using the 20 Volt process).

Above and below each tile is a clear field area which is reserved for user defined thin film resistors. Interspersed between the tiles and around the periphery of the array are the various components available on the array. To accommodate rapid layout, allSP1204 components are positioned on a 15u grid. Within the clear field area there is a 5u sub grid for thin-film resistor layout. It is symmetric about the two perpendicular center lines of the array. There are additional symmetries within the tiles themselves as well as between adjacent tiles. The dimensions of the SP1204 are 140 mils x 146 mils. The S P1204 array is available in two process options: 20 Volt and 35 Volt processes. By controlling substrate resistivity, VCEO's of 35 Volts & 20 Volts are achieved. The 20 Volt VCEO process offers somewhat lower parasitics, and therefore, higher speed. This is the preferred process for high speed applications, if maximum voltages can be held below 20 Volts.