SP8400KGMPES

The SP8400KGMPES is designed as a very low phase noise programmable divider which is based on a divide by 8/9 dual modulus prescaler and a 12 stage control counter. This gives a minimum division ratio of 56 (64 for fractional - N synthesis applications), and a maximum division ratio of 4103. Special circuit techniques have been used to reduce the phase noise considerably below that produced by standard dividers. The data inputs are CMOS or TTL compatible. It is packaged in a 28 pin plastic SO package.

SP8400KGMPES has two features. (1) It has very low phase noise (typically -156 dBc / Hz at 1kHz offset). (2) Supply voltage 5V. That are all the main features.

Some absolute maximum ratings of SP8400KGMPES have been concluded into several points as follow. (1) Its supply voltage would be 6.5V. (2) Its output current would be 20mA. (3) Its storage temperature range would be from -55°C to +125°C. (4) Its maximum clock input voltage would be 2.5V p-p. That are all the main ratings and it should be noted that stresses above those listed in absolute maximum ratings may cause permanent damage to device.

Also some electrical characteristics of SP8400KGMPES(guaranteed over: supply voltage VCC = +4.75V to +5.25V temperature Tamb = -10°C to +75°C and tested at +4.75V and +5.25V at Tamb = +25°C) about it. (1) Its supply current would be min 122mA and typ 137mA and max 152mA. (2) Its output voltage swing would be min 320mV and typ 410mV. (3) Its input sensitivity 200MHz to 1.5GHz would be max 140mV. (4) Its logic high voltage would be min 2.2V. (5) Its loic low voltage would be max 0.8V. (6) Its input current would be max 180uA with condition of data input voltage 5V. And so on. At present we have not got so much information about it. And we would try hard to get more. If you have any question or suggestion or want to know more information please contact us for details. Thank you!