SPI-4

The Optical Interworking Forum's (OIF) SPI- 4 Phase 1 interface allows the interconnection of Physical Layer devices to Link Layer devices in 10Gb/s ATM, POS, and Ethernet applications. Modelware's SPI-4 Phase 1 core performs the interface functions on both sides of the interface as shown in Figure 1and Figure 2.

On the system side, the SPI-4 Phase 1 core interfaces to a single or to multiple links or ports via Altera's Atlantic interface.

The Spi4Tx block monitors the Source FIFOs fill level and the flow control information received from the opposite side of the SPI-4 interface. If a Source FIFO has data and the flow control information for the corresponding channel indicates that it is ready to accept data, the Spi4Tx block initiates a data transfer from the Source FIFO towards the SPI-4 interface.

The Spi4Rx block transmits the Sink FIFO status information to the opposite side according to the Sink FIFO almost-full flags.

The SPI-4 block stores data received for a particular link in that link's FIFO. Sink FIFO flags indicate to the user the presence of data in the FIFO(s).