SST-Melody

Internal Supply Voltage (V_DDINT) . . . . . . . . . 0.3 V to +3.0 V
Internal Supply Voltage (V_DDEXT) . . . . . . . . . 0.3 V to +4.0 V
Input Voltage² . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +4.0 V
Output Voltage Swing³ . . . . . . . . . . 0.5 V to V_DDEXT + 0.5 V
Operating Temperature Range . . . . .  . . . . 40°C to +85°C
Storage Temperature Range . . . . . . . . . . 65°C to +150°C
Lead Temperature (5 sec) LQFP . . . . . . . . .  . . . . . . . . 280°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2Applies to bidirectional pins (D0D3, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1A13, PF0PF7) and input only pins (CLKIN, RESET, BR, DR0, DR1, PWD)
3Applies to output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL20, BGH)

The SST-Melody-DAP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The SST-Melody-DAP combines the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, flag I/O, extensive interrupt capabilities, and on-chip program and data memory.

The SST-Melody-DAP integrates 80 Kbytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The SST-Melody-DAP is available in a 100-lead LQFP package and 144-ball mini-BGA.

In addition, the SST-Melody-DAP supports new instructions, which include bit manipulations-bit set, bit clear, bit toggle, bit test-new ALU constants, new multiplication instruction (x squared), biased rounding, result-free ALU operations, I/O memory transfers, and global interrupt masking, for increased flexibility. Fabricated in a high speed, low power, CMOS process, the SST-Melody-DAP operates with a 13.3 ns instruction cycle time. Every instruction can execute in a single processor cycle.

The SST-Melody-DAP's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the SST-Melody- DAP can:

• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer