SST28LP040

The SST28LP040 is organized as a 512K x 8 (bits) common memory array plus a 1K x 8 attribute memory array. The attribute memory can be accessed by asserting REG# or issuing an Enable_Attribute command. Either one nibble or two nibbles in a byte can be read in one cycle with internal decoding of CEL#, CEH#, and HB. The 28LP040 must be configured as a pair per 1Mbyte of PCMCIA application memory. Each byte in the PCMCIA memory map consists of two nibbles, one from each 28LP040 in the pair.

Each SST28LP040 has 4M bits of common memory and 8K bits of attribute memory and is manufactured using SST's proprietary, high performance CMOS SuperFlash EEPROM Technology. The split gate cell design and thick oxide tunneling i njector attain better reliability and manufacturability compared with alternative approaches. The 28LP040 erases and programs with a 3.0 volt only power supply. (VCC: 3.0V to 3.6V)

Figure 1 shows the functional blocks of the SST28LP040, and shows the memory map consisting of common memory array and the attribute memory array. Figure 2 shows the pin assignments for the TSOP package. Pin description and operation modes are described in Tables 1 through 6.