Features: • Flash Organization: 1M x16
16 Mbit: 12 Mbit + 4 Mbit
• Concurrent Operation
Read from or Write to SRAM while Erase/Program Flash
• SRAM Organization:
2 Mbit:128K x16
4 Mbit: 256K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption: (typical values @ 5 MHz)
Active Current: Flash 10 mA (typical) SRAM 6 mA (typical)
Standby Current: 10 A (typical)
• Hardware Sector Protection (WP#)
Protects 4 outer most sectors (4 KWord) in the larger bank by holding WP# low and unprotects by holding WP# high
• Hardware Reset Pin (RST#)
Resets the internal state machine to reading data array
• Sector-Erase Capability
Uniform 2 KWord sectors
• Block-Erase Capability
Uniform 32 KWord blocks
• Read Access Time
Flash: 70 ns
SRAM: 70 ns
• Erase-Suspend / Erase-Resume Capabilities
• Latched Address and Data
• Fast Erase and Word-Program (typical):
Sector-Erase Time: 18 ms
Block-Erase Time: 18 ms
Chip-Erase Time: 35 ms
Program Time: 7 s
• Automatic Write Timing
Internal VPP Generation
• End-of-Write Detection
Toggle Bit
Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Packages Available
48-ball LFBGA (6mm x 8mm)
48-ball LBGA (10mm x 12mm)
Non-Pb (lead-free) packages availableSpecificationsOperating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0W
Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . "with-Pb" units2: 240°C for 3 seconds
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "non-Pb" units: 260°C for 3 seconds
Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
1. VDD = VDDF and VDDS
2. Certain "with-Pb" package types are capable of 260°C for 3 seconds; please consult the factory for the latest information.
3. Outputs shorted for no more than one second. No more than one output shorted at a time.
DescriptionThe SST34HF164G ComboMemory devices integrate a 1M x16 CMOS flash memory bank with either 128K x16 or 256K x16 CMOS SRAM memory bank in a multi-chip package (MCP). These devices are fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches.
The SST34HF164G devices are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF164G devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Program time of 7 sec. The entire flash memory bank can be erased and programmed word-by-word in 4 seconds (typically) for the SST34HF16xG, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF16xG devices contain on-chip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals.
The SRAM bank enable signal, BES#, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. See Figure 1 for memory organization.
SST34HF164G Data Sheet
