SST34HF1681

`Flash Organization: 1M x16
`Dual-Bank Architecture for Concurrent
  Read/Write Operation
  --16 Mbit: 12 Mbit + 4 Mbit
`SRAM Organization:
  --8 Mbit: 512K x16
`Single 2.7-3.3V Read and Write Operation
`Superior Reliability
  --Endurance: 100,000 Cycles (typical)
  --Greater than 100 years Data Retention
`Low Power Consumption:
  --Active Current:  25 mA (typical)
  --Standby Current:  20A (typical)
`Hardware Sector Protection (WP#)
  --Protects 4 outer most sectors (4 KWord) in the
     larger bank by holding WP# low and unprotects
     by holding WP# high
`Hardware Reset Pin (RST#)
  --Resets the internal state machine to reading data array
`Sector-Erase Capability
  --Uniform 1 KWord sector
`Block-Erase Capability
  --Uniform 32 KWord block
`Read Access Time
  --Flash: 70 and 90 ns
  --SRAM: 70 and 90 ns
`Latched Address and Data
`Fast Erase and Word-Program:
  --Sector-Erase Time: 18 ms (typical)
  --Block-Erase Time: 18 ms (typical)
  --Chip-Erase Time: 70 ms (typical)
  --Word-Program Time: 14s (typical)
  --Chip Rewrite Time: 8 seconds (typical)
`Automatic Write Timing
  --Internal Vpp  Generation
`End-of-Write Detection
  --Toggle Bit
  --Data# Polling
  --Ready/Busy# pin
`CMOS I/O Compatibility
`JEDEC Standard Command Set
`Conforms to Common Flash Memory Interface  (CFI)
`Packages Available
  --56-ball LFBGA (8mm x 10mm)

    The SST34HF1681 ComboMemory devices integrate a 1M x16 CMOS flash memory bank with a 512K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP). These devices are fabricated using SST's proprietary, high performance CMOS SuperFlash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF1681 devices are ideal for applications such as cellular phones, GPSs, PDAs and other portable electronic devices in a low power and small form factor system.

    The SST34HF1681 features dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the SRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 4 Mbit and 12 Mbit with top or bottom sector protection options for storing boot code, program code, configuration/parameter data and user data.

    The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase nd Program times increase with accumulated Erase/Pro-gram cycles. The SST34HF1681 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high performance Word-Program, the flash memory banks provide a typical Word-Pro- gram time of 14 |ìsec. The entire flash memory bank cabe erased and programmed word-by-word in typically 8 seconds for the SST34HF1681, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inad vertent flash write, the SST34HF1681 devices contain on chip hardware and software data protection schemes.

    The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signal, BES1# and BES2, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. 

    Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF1681 are offered in both commercial and extended temperatures and a small footprint package to meet board space con straint requirements.