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SST49LF004B

Features: • SST49LF004B: 512K x8 (4 Mbit)• Conforms to Intel LPC Interface Specification 1.1 Supports Single-Byte LPC Memory and Firmware Memory Cycle Types• Flexible Erase Capability Uniform 4 KByte sectors Uniform 64 KByte overlay blocks Chip-Erase for PP Mode Only• S...

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SST49LF004B: Features: • SST49LF004B: 512K x8 (4 Mbit)• Conforms to Intel LPC Interface Specification 1.1 Supports Single-Byte LPC Memory and Firmware Memory Cycle Types• Flexible Erase Capabi...

SST49LF004B Data Sheet

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Part Number:
SST49LF004B
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• SST49LF004B: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification 1.1
   Supports Single-Byte LPC Memory and Firmware Memory Cycle Types
• Flexible Erase Capability
   Uniform 4 KByte sectors
   Uniform 64 KByte overlay blocks
   Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
   Endurance: 100,000 Cycles (typical)
   Greater than 100 years Data Retention
• Low Power Consumption
   Active Read Current: 6 mA (typical)
   Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
   Sector-Erase Time: 18 ms (typical)
   Block-Erase Time: 18 ms (typical)
   Chip-Erase Time: 70 ms (typical)
   Byte-Program Time: 14 µs (typical)
   Chip Rewrite Time: 8 seconds (typical)
• Two Operational Modes
   Low Pin Count (LPC) interface mode for in-system operation
   Parallel Programming (PP) mode for fast production programming
• LPC Interface Mode
   5-signal LPC bus interface supporting byte Read and Write
   33 MHz clock frequency operation
   WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block
   Block Locking Registers for individual block write-lock and lock-down protection
   JEDEC Standard SDP Command Set
   Data# Polling and Toggle Bit for End-of-Write detection
   5 GPI pins for system design flexibility
   4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
   11-pin multiplexed address and 8-pin data I/O interface
   Supports fast programming in-system on programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
   32-lead PLCC
   40-lead TSOP (10mm x 20mm)


Pinout

Connection Diagram


Specifications

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA


Description

The SST49LF004B flash memory device is designed to interface with host controllers (chipsets) that support a lowpin- count (LPC) interface for BIOS applications. The SST49LF004B device complies with Intel's LPC Interface Specification 1.1, supporting single-byte Firmware Memory and LPC Memory cycle types.

The SST49LF004B is backward compatible to the SST49LF00xA Firmware Hub and the SST49LF0x0A LPC Flash. In this document, FWH mode in the SST49LF00xA specification is referenced as the Firmware Memory Read/ Write cycle and LPC mode in the SST49LF0x0A specification is referenced as the LPC Memory Read/Write cycle. Two interface modes are supported by the SST49LF004B: LPC mode (Firmware Memory and LPC Memory cycle types) for in-system operations and Parallel Programming (PP) mode to interface with programming equipment.

The SST49LF004B flash memory device is manufactured with SST's proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain greater reliability and manufacturability compared with alternative approaches. The SST49LF004B device significantly improves performance and reliability, while lowering power consumption. The SST49LF004B device writes (Program or Erase) with a single 3.0-3.6V power supply.

The SST49LF004B provides a maximum Byte-Program time of 20 µsec. The entire memory can be erased and programmed byte-by-byte in 8 seconds when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent writes, the SST49LF004B device has on-chip hardware and software write protection schemes. It is offered with a typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST49LF004B uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any given voltage range the SuperFlash technology uses less current to pro-




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