SST49LF030A

The SST49LF030A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance appl cation in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment.

The SST49LF030A flash memory device is manufactured with SST's proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF030A device significantly iproves performance and reliability, while lowering power consumption. The SST49LF030A device writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. For any give voltage range, the SuperFlash technology uses less current to program and has a shorter erase time; the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF030A product  provides a maximum Byte-Program time of 20 sec. The entire memory can be erased and programmed byte-bybyte typically in 6 seconds when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed.

Therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of Erase cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST49LF030A device is offered in 32-lead TSOP and 32- lead PLCC packages. See Figures 1 and 2 for pin assignments and Table 1 for pin descriptions.