ST10F280

Maximum Clock Frequency :
Program Memory Size :
Data RAM Size :
On-Chip ADC :
Operating Supply Voltage :
Operating Temperature Range :
Package / Case :
Mounting Style :
Data Bus Width : 16 bit
Core : ST10
Processor Series : ST10F28x


Specifications

Symbol	Parameter	Value	Unit
VDD	Voltage on VDD pins with respect to ground1	-0.5, +6.5	V
VIO	Voltage on any pin with respect to ground1	-0.5, (VDD +0.5)	V
VAREF	Voltage on VAREF pin with respect to ground1	-0.3, (VDD +0.3)	mA
IOV	Input Current on any pin during overload condition1	-10, +10	mA
ITOV	Absolute Sum of all input currents during overload condition1	|100 mA|	mA
Ptot	Power Dissipation1	1.5	W
TA	Ambient Temperature under bias	-40, +125	°C
Tstg	Storage Temperature1	-65, +150	°C

Note: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V_IN > V_DD or V_IN < V_SS ) the voltage on pins with respect to ground (VSS ) must not exceed the values defined by the Absolute Maximum Ratings.

Description

The ST10F280 is a new derivative of the ST Microelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage FLASH memory, on-chip high-speed RAM, and clock generation via PLL.

ST10F280 is processed in 0.35mm CMOS technology. The MCU core and the logic is supplied with a 5V to 3.3V on chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V.

The ST10F280 is upward compatible with the ST10F269 device, with the following set of differences:
Two supply pins (DC1,DC2) on the PBGA-208 package are used for decoupling the internally generated 3.3V core logic supply. Do not connect these two pins to 5.0V external supply. Instead, these pins should be connected to a decoupling capacitor (ceramic type, value  330nF).

The A/D Converter characteristics stay identical but 16 new input channel are added. A bit in a new register (XADCMUX) control the multiplexage between the first block of 16 channel (on Port5) and the second block (on XPort10). The conversion result registers stay identical and the software management can determine the block in use. A new dedicated timer controls now the ADC channel injection mode on the input CC31 (P7.7). The output of this timer is visible on a dedicated pin (XADCINJ) to emulate this new functionnality.

A second XPWM peripheral (4 new channels) is added. Four dedicated pins are reserved for the outputs (XPWM[0:3])

A new general purpose I/O port named XPORT9 (16 bits) is added. Due to the bit addressing management, ST10F280 will be different from other standard general purpose I/O ports.