ST14C04C

Features: · 1,000,000 ERASE/WRITE CYCLES MINIMUM· OVER 10 YEARS DATA RETENTION· SINGLE 3V to 5.5V POWER SUPPLY· TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE· BYTE and MULTIBYTE WRITE (UP TO 4 BYTES)· PAGE WRITE (UP TO 8 BYTES)· BYTE, RANDOM and SEQUENTIAL READ MODES· SELF TIMED PROGRAMMING ...

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ST14C04C Picture
SeekIC No. : 004506232 Detail

ST14C04C: Features: · 1,000,000 ERASE/WRITE CYCLES MINIMUM· OVER 10 YEARS DATA RETENTION· SINGLE 3V to 5.5V POWER SUPPLY· TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE· BYTE and MULTIBYTE WRITE (UP TO 4...

floor Price/Ceiling Price

Part Number:
ST14C04C
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/23

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Product Details

Description



Features:

· 1,000,000 ERASE/WRITE CYCLES MINIMUM
· OVER 10 YEARS DATA RETENTION
· SINGLE 3V to 5.5V POWER SUPPLY
· TWO WIRE SERIAL INTERFACE, FULLY I2C
    BUS COMPATIBLE
· BYTE and MULTIBYTE WRITE (UP TO 4 BYTES)
· PAGE WRITE (UP TO 8 BYTES)
· BYTE, RANDOM and SEQUENTIAL READ MODES
· SELF TIMED PROGRAMMING CYCLE
· AUTOMATIC ADDRESS INCREMENTING
· GUARANTEED 4KV ESD PROTECTION,USING HUMAN BODY MODEL



Description

The ST14C04C is a 4K bit electrically erasable programmable memory (EEPROM), organized as 2 blocks of 256 x 8 bits. It is manufactured in SGSTHOMSON's Hi-Endurance Advanced CMOS technology which confirms an endurance of more than 1,000,000 erase/write cycles with a data retention of over 10 years. This memory operates with a supply voltage value as low as 3V.

The memory of the ST14C04C is compatible with the I2C standard, two wire, serial interface which uses a bi-directional data bus and serial clock.

It carries a built-in 7 bit, unique device identification code (1010000) corresponding to the I2C bus definition. Only one memory can be attached to the I2C bus. This memory behaves as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010000), plus one read/write bit and terminated by an acknowledge bit.

When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition.

Both wafers (sawn or unsawn) and micromodules (on film) of the ST14C04C are available.




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