ST16CF54

 8 BIT ARCHITECTURE CPU 16 KBytes of USER ROM SECTOR
COMBINATIVE 8 KBytes of SYSTEM ROM 512 Bytes of RAM 4 KBytes of EEPROM, SECTOR
COMBINATIVE 512 BITS MODULAR ARITHMETIC
PROCESSOR
Fast modular multiplication and squaring us-ing Montgomery method
Driven by STMicroelectronics cryptographiclibrary EFFICIENT CRYPTOGRAPHIC LIBRARY

 EFFICIENT CRYPTOGRAPHIC LIBRARY
Embedded software for driving the MAP
 through a set of advanced functions
Supports modular and non modular arithme-tic
Operand length can be any size up to 1024bits
Highly reliable CMOS EEPROM technology
10 year data retention
100,000 Erase/Write cycle endurance
Protected One Time Programmable block (32or 64 Bytes)
Separate Write and Erase cycle for fast "1"
 programming
1 to 32 Bytes block either Erase or Write in
 single cycle programming SERIAL ACCESS, ISO 7816-3 COMPATIBLE SINGLE 5V ±10% SUPPLY VOLTAGE STANDBY MODE FOR POWER SAVING

UP TO 5 MHz INTERNAL OPERATING
    FREQUENCY

 VERY HIGH SECURITY FEATURES
   INCLUDING EEPROM FLASH ERASE

CONTACT ASSIGNMENT COMPATIBLE ISO
   7816-2

The ST16CF54 Level B, a member of the ST16 device family, is a serial access microcontroller especially designed for high volume and cost competitive Smartcard applications, where high performance Public Key Algorithms will be imple- mented, to cut down initialization and communica- tion costs and to increase security.

Its internal Modular Arithmetic Processor ST16CF54 is de- signed to speed up cryptographic calculations re- quired in Public Key Algorithms. It processes hardware modular multiplication and squaring on various size 32/256/288/384/416/512 bits oper- and. By using of software (cryptographic firmware library) this calculation can be extended for any size of operand from 3 to 1024 bits.

The ST16CF54 Level B is based on an ST 8 bit CPU core including on-chip memories: 512 Bytes of RAM, 16 KBytes of USER ROM and 4 KBytes of EEPROM. Both ROM and EEPROM memories can be con- figured into two sectors. Access rules from any memory section (sector) to another are setup by the User defined Memory Access Control Matrix.In addition, to reinforce the security of this product, an hardware mechanism called SRAC (SYSTEM ROM Access Control) has been implemented. It protects against unauthorized access to both SYSTEM ROM and MAP. Reliability data related to the ST16CF54 Level B product, manufactured using ST's advanced CMOS EEPROM technology, confirm data reten- tion of up to 10 years and endurance up to100,000 Erase/Write cycles. As all other ST16 family members, it is fully com- patible with the ISO standards for Smartcard ap- plications. Software development and firmware (ROM code, options) generation are completed by the ST16- 19HDS development system.

The ST16CF54 Level B can be delivered either as unsawn or sawn wafers, 180 or 275 micron thick- ness as well as in micromodule package.