ST18952

• four independent DMA channels
• transfers on X / Y / I spaces (simultaneous transfers on X and Y spaces)
• cycle stealing operation:
            • 3 cycles for a single data transfer (+1cycle for transfers on I space)
            • (n+2) cycles for an n-data block transfer (+1cycle for transfers on I space)
• each channel has:
         • 3 signals: request (DMARQ), acknowledge (DMACK), interrupt request (DIT)
         • 4x16 bit registers for block transfer facilities
• fixed priority between the four channels (highest channel 0, lowest channel 3)