PinoutSpecifications Symbol Parameter Value Unit VDD Supply Voltage (Note 1) 15 V VSS Supply Voltage (Note 1) -15 V VCC Supply Voltage (Note 1) 7 V VI Input Voltage Range (DRIVER) -0.3 to (VCC+0.3) V VI Input Voltage Range (RECEIVER) -30 to 30 V VO Output ...
ST75C185: PinoutSpecifications Symbol Parameter Value Unit VDD Supply Voltage (Note 1) 15 V VSS Supply Voltage (Note 1) -15 V VCC Supply Voltage (Note 1) 7 V VI Input Voltage Ran...
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| Symbol | Parameter | Value | Unit |
| VDD | Supply Voltage (Note 1) | 15 | V |
| VSS | Supply Voltage (Note 1) | -15 | V |
| VCC | Supply Voltage (Note 1) | 7 | V |
| VI | Input Voltage Range (DRIVER) | -0.3 to (VCC+0.3) | V |
| VI | Input Voltage Range (RECEIVER) | -30 to 30 | V |
| VO | Output Voltage Range (DRIVER) | (VSS-6) to (VDD+6) | V |
| VO | Output Voltage Range (RECEIVER) | -0.3 to (VCC+0.3) | V |
| IO | Receiver Low Level Output Current | 20 | mA |
| TA | Operating Free-Air Temperature Range | -40 to 85 | °C |
| Tstg | Storage Temperature Range | -65 to +150 | °C |
| TL | Lead Temperature 1.6mm from case for 10 sec | 260 | °C |
The ST75C185 is low power BICMOS device containing three independent drivers and five receivers that is used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device has been designed to conform to Standards ANSI/EIA-232-E. The drivers have a controlled output slew rate that is limited to a maximum of 30V/s and the receivers have filters that reject input noise pulses that are shorter than 1s. Both these features eliminate the need of external components.
The ST75C185 hasn't a power sequence fault condition. It has been designed using low-power techniques in a BICMOS tecnology.
In most application the receivers of the ST75C185 contained in this device will interface to single inputs peripheral devices such as ACEs, UARTs or microprocessors. By using sampling, such peripheral devices are usuallly insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the ST75C185 receiver outputs be buffered by single gates of the HCMOS, ALS or 74F logic families.