STC3500

Features:

• Complies with Telcordia GR-1244-CORE, GR-253-CORE, and ITU-T G.812/G.813
• Supports Master/Slave operation
• Supports Free Run, Locked, and Hold Over modes
• Accepts 8 reference inputs from 8 kHz to 77.76 MHz and one 8 kHz cross reference
• Continuous input reference quality monitoring
• Input reference frequencies are automatically detected
• Automatic or manual selection for active reference
• Supports hardwire pins to select active reference
• Four output signals: one selectable up to 155.52 MHz, one fixed at 8 kHz, one multiframe sync fixed at 2 kHz,
  and 1.544 MHz or 2.048 MHz BITS output
• Output phase is adjustable in slave mode
• Frequency ramp control during reference switching
• Hit-less reference switching
• Configurable bandwidth filter
• Supports SPI and 8-bit parallel bus interface
• IEEE 1149.1 JTAG boundary scan
• Available in FBGA144 package


Specifications

Symbol	Parameter	Minimum	Nominal	Maximum	Units	Notes
Vdd2.5	Logic power supply voltage, 2.5V	-0.3	-	3.0	Volts	1
Vdd3.3	Logic power supply voltage 3.3V	-0.3	-	4.0	Volts	1
AVdd2.5	Analog power supply voltage, 2.5V	-0.3	-	4.0	Volts	1
VIN	Logic input voltage, rel. to GND	-0.3	-	Vdd3.3 + 0.5	Volts	1
TSTG	Storage temperature	-55	-	110		1

Note 1: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to 
             the device. Exposure to absolute maximum rated conditions for extended periods may affect
             device  reliability. Devices should not be operated outside the Recommended Operating Conditions.


Description

The STC3500 is an integrated single chip solution for the Synchronous Timing Source in SONET/SDH network elements. The device generates four synchronous clocks, including BITS, and is fully compliant with Telcordia GR-1244-CORE, GR-253-CORE and ITU-T G.812/G.813.

The STC3500 can operate in Free Run, locked or Hold Over mode. In the Free Run mode, it locks on an OCXO or TCXO. In the locked mode, it locks on one of 8 input reference clocks. The frequency of each input
reference clock can be user selected or automatically detected by the device. The active reference can be automatically selected by the device based on a priority table or manually controlled by the user. All reference switches are hit-less. In Hold Over mode, the device generates outputs based on the frequency history of the last locked reference.

The STC3500 supports the Master or Slave mode of operation for redundant designs. In master mode, the device operates in Free Run, locked or Hold Over. In slave mode, the output clocks are locked to the master's primary Sync_Clk or 8 kHz synchronous clock output and are phase offset adjustable. Parallel or serial bus interfaces are provided to access STC3500 internal control and status registers.

Major operations can be performed from either the bus interface or external hardwire pins.