STEL1109CR

Features: ` Complete BPSK/QPSK/16QAM modulator in a CMOS ASIC` Programmable over a wide range of data rates` NCO modulator provides fine frequency resolution` 165 MHz maximum clock rate generates a modulated carrier at frequencies programmable from 5 to 65 MHz` Operates in continuous and burst mod...

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STEL1109CR Picture
SeekIC No. : 004507580 Detail

STEL1109CR: Features: ` Complete BPSK/QPSK/16QAM modulator in a CMOS ASIC` Programmable over a wide range of data rates` NCO modulator provides fine frequency resolution` 165 MHz maximum clock rate generates a ...

floor Price/Ceiling Price

Part Number:
STEL1109CR
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/14

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Product Details

Description



Features:

` Complete BPSK/QPSK/16QAM modulator in a CMOS ASIC
` Programmable over a wide range of data rates
` NCO modulator provides fine frequency resolution
` 165 MHz maximum clock rate generates a modulated carrier at frequencies programmable from 5 to 65 MHz
` Operates in continuous and burst modes
` Differential Encoder, Programmable Scrambler, and Programmable Reed-Solomon FEC Encoder
` Programmable 32-tap FIR Filter for signal shaping before modulation
` 10-bit DAC implemented on chip
` Complete upstream modulator solution serial data in and RF signal out
` Compatible with DAVIC, IEEE 802.14 (preliminary), Intelsat IESS-308, ITU J.83 Annex A, MCNS Standards
` Supports low data rates for voice applications and high data rates for wideband applications
` Small Footprint, Surface Mount 80-Pin MQFP Package




Specifications

Symbol
Parameter
Range
Units Note 1
Tstg
Storage Temperature
-40 to +125
°C
VDDmax
Supply voltage on VDD
-0.3 to +4.6
volts
AVDDmax
Supply voltage on AVDD
-0.3 to +4.6
volts
5VDDmax
Supply voltage on 5VDD
-0.3 to +7.0
volts Note 2
AVSS
Analog supply return for AVDD
±10% of VDD
volts
VI(max)
Input voltage
-0.3 to VDD+0.3
volts
Ii
DC input current
± 30
mA
PDiss (max)
Power dissipation @ 85oC
690
mW Note 3


Note:
1. All voltages are referenced to VSS.
2. 5VDD must be greater than or equal to VDD. This rule can be violated for a maximimum of 100 msec during power up.
3. See Duty Cycle Derating Curves (Figure 15)




Description

The STEL-1109 is comprised of the Data Path and Control Unit sections shown in Figure 1. The Data Path is comprised of a Bit Sync Block, Bit Encoder Block (i.e.,Êthe Scrambler, Reed-Solomon Encoder, and two Multiplexers shown in Figure 2), Symbol Mapper Block (i.e., the Bit Mapper, Differential Encoder, and Symbol Mapper are shown in FigureÊ5), two channels (one for I and one for Q), a Combiner, and a 10-bit DAC. Each channel consists of a Nyquist Filter, Interpolation Filter, and Modulator. The Control Unit is comprised of a Bus Interface Unit (BIU), Clock Generator, and NCO.




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