Features: SINGLECHIP2B1QLINECODETRANSCEIVERSUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONSMEETS OR EXCEEDS ETSI EUROPEAN STANDARDSINGLE 5V SUPPLYDIP28 AND PLCC44 PACKAGEHCMOS3A SGS-THOMSON ADVANCED 1.2mm DOUBLE-METAL CMOS PROCESSROUND TRIP DELAY MEASUREMENTEXTENDED TEMPERATURE RANGE (-40°C TO +...
STLC5412: Features: SINGLECHIP2B1QLINECODETRANSCEIVERSUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONSMEETS OR EXCEEDS ETSI EUROPEAN STANDARDSINGLE 5V SUPPLYDIP28 AND PLCC44 PACKAGEHCMOS3A SGS-THOMSON ADVANC...
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| Symbol | Parameter | Value | Unit |
| VCC | Supply Voltage | 0.3 to 7.0 | V |
| VIN | Input Voltage | 0.3 to 7.0 | V |
| TA | Operting Temperature Range | -40 to 85 (3) | °C |
| Tstg | Storage Temperature Range | 55 to 150 | °C |
STLC5412 is a complete monolithic transceiver for ISDN Basic access data transmission on twisted pair subscriber loops typical of public switched telephone networks. The device is fully compatible with ETSI ETRO80 and CSE (C32-11) French specifications.
The equivalent STLC5412 of 160 kbit/s full-duplex transmission on a single twisted pair is provided, according to the formats defined in the a.m. spec.Frames include two B channels, each of 64 kbit/s,one D channel of 16 kbit/s plus an additional 4 kbit/s M channel for loop maintenance and other user functions. 12 kbit/s bandwidth is reserved for framing. 2B1Q Line coding is used, where pairs of bits are coded into one of 4 quantumlevels. This technique results in a low frequency spectrum (160 kbit/s turn into 80 kbaud), thereby reducing both line attenuation and crosstalk and achieving long range with low Bit Error Rates.
STLC5412 is designed to operate with Bit Error Rate near-end Crosstalk (NEXT) as specified in european ETSI recommendation.To meet these very demanding specifications, the device includes two Digital Signal Processors,one configured as an adaptive Echo-Canceller to cancel the near end echoes resulting from the transmit/receive hybrid interface, the other as an adaptive line equalizer. A Digital Phase-Locked Loop (DPLL) timing recovery circuit is also included that provides in NT modes a 15.36 MHz synchronized clock to the system. Scrambling and descrambling are performed as specified in the specifications.
On the system side, STLC5412 can be linked to two bus configuration simply by pin MWbias.