Features: · MEETS OR EXCEEDS THE REQUIREMENTS OF ANSI TIA/EIA-644 STANDARD· OPERATES WITH A SINGLE 3.3V SUPPLY· DESIGNED FOR SIGNALING RATE UP TO 400Mbps· DIFFERENTIAL INPUT THRESHOLDS ±100mV MAX· TYPICAL PROPAGATION DELAY TIME OF 2.5ns· POWER DISSIPATION 60mW TYPICAL PER RECEIVER AT 200MHz· LOW V...
STLVDS9637: Features: · MEETS OR EXCEEDS THE REQUIREMENTS OF ANSI TIA/EIA-644 STANDARD· OPERATES WITH A SINGLE 3.3V SUPPLY· DESIGNED FOR SIGNALING RATE UP TO 400Mbps· DIFFERENTIAL INPUT THRESHOLDS ±100mV MAX· T...
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|
Symbol |
Parameter |
Value |
Unit | |
|
VCC |
Supply Voltage (Note 1) |
-0.5 to 4.6 |
V | |
|
VI |
Input Voltage |
-0.5 to (VCC + 0.5) |
V | |
|
VI |
Input Voltage (A or B inputs) |
-0.5 to 4.6 |
V | |
|
ESD |
Human Body Model | Pins Receivers |
7 |
KV |
| All Pins vs GND |
3 | |||
|
Tstg |
Storage Temperature Range |
-65 to +150 |
||
The STLVDS9637, is a differential line receiver that implements the electrical characteristics of low voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operations with a 3.3V supply rail. This differential receiver provides a valid logical output state with a 3.3V supply rail. STLVDS9637 also provides a valid logical output state with a ±100mV differential input voltage within the input common mode voltage range. The input common mode voltage allows 1V of ground potential difference between two LVDS nodes.
The intended application of this device STLVDS9637 and signalling technique is both point-to-point and multidrop data transmission over controlled impedance media approximately 100. The transmission media may be printed circuit board traces, backplanes or cables. The ultimate rate and distance of data transfer depend upon the attenuation characteristics of the media and noise coupling to the environment.
The STLVDS9637 version is characterized for operation from -40 to 85.