STN3NE06

MOSFET USE 511-STN3NF06

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SeekIC No. : 00164999 Detail

STN3NE06: MOSFET USE 511-STN3NF06

floor Price/Ceiling Price

Part Number:
STN3NE06
Mfg:
STMicroelectronics
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/14

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Product Details

Quick Details

Transistor Polarity : N-Channel Drain-Source Breakdown Voltage : 60 V
Gate-Source Breakdown Voltage : +/- 20 V Continuous Drain Current : 3 A
Resistance Drain-Source RDS (on) : 0.1 Ohms Configuration : Single Dual Drain
Maximum Operating Temperature : + 150 C Mounting Style : SMD/SMT
Package / Case : SOT-223 Packaging : Reel    

Description

Transistor Polarity : N-Channel
Gate-Source Breakdown Voltage : +/- 20 V
Mounting Style : SMD/SMT
Packaging : Reel
Maximum Operating Temperature : + 150 C
Drain-Source Breakdown Voltage : 60 V
Package / Case : SOT-223
Continuous Drain Current : 3 A
Configuration : Single Dual Drain
Resistance Drain-Source RDS (on) : 0.1 Ohms


Features:

 TYPICAL RDS(on) = 0.08
EXCEPTIONAL dv/dt CAPABILITY
AVALANCHERUGGED TECHNOLOGY
100 % AVALANCHETESTED
APPLICATION ORIENTED CHARACTERIZATION



Application

DC MOTOR CONTROL (DISK DRIVES,etc.)
DC-DC & DC-AC CONVERTERS
SYNCHRONOUS RECTIFICATION



Specifications

Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 60 V
VDGR Drain-gate Voltage (RGS = 20 k ) 60 V
VGS Gate- source Voltage ± 20 V
ID Drain Current (continuos) at TC = 25
3 A
ID Drain Current (continuos) at TC = 100 1.8 A
IDM() Drain Current (pulsed) 12 A
PTOT Total Dissipation at TC = 25 2.5 W
  Derating Factor 0.02 W/
dv/dt (1) Peak Diode Recovery voltage slope 6 V/ns
Tstg Storage Temperature 65 to 150
Tj Max. Operating Junction Temperature 150

(•) Pulse width limited by safe operating area (1) ISD  12 A, di/dt  200 A/s, VDD  V(BR)DSS, Tj TJMAX New RDS (on) spec. starting from JULY 98




Description

This Power Mosfet is the latest development of STN3NE06 STMicroelectronics unique "Single Feature Size]" stip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.




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