MOSFET 20V 34A 8.3W
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Transistor Polarity : | N-Channel | Drain-Source Breakdown Voltage : | 20 V | ||
Gate-Source Breakdown Voltage : | +/- 20 V | Continuous Drain Current : | 34 A | ||
Resistance Drain-Source RDS (on) : | 4.3 mOhms | Configuration : | Single | ||
Maximum Operating Temperature : | + 175 C | Mounting Style : | SMD/SMT | ||
Package / Case : | TO-252-3 | Packaging : | Reel |
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
Static | |||||
Gate Threshold Voltage | VGS(th) | VDS = VGS, ID = 250 A | 1.7 | V | |
On-State Drain Currenta | ID(on) | VDS =5 V, VGS = 10 V | 1190 | A | |
Drain-Source On-State Resistancea | rDS(on) | VGS = 10V, ID = 20A | 0.0035 | 0.0035 | |
VGS = 10 V, ID = 20A, TJ = 125°C | 0.0048 | ||||
VGS = 4.5 V, ID = 20 A | 0.0049 | 0.0048 | |||
Forward Transconductancea |
gfs |
VDS = 15 V, ID = 20 A |
68 |
S | |
Forward Voltagea | VSD | IS= 50A, VGS = 0 V | 0.91 | 0.90 | V |
Dynamicb | |||||
Input Capacitance | Ciss | VGS = 0 V, VDS =10 V, f = 1 MHz | 4807 | 5000 | Pf |
Output Capacitance | Coss | 1664 | 1650 | ||
Reverse Transfer Capacitance | Crss | 641 | 770 | ||
Total Gate Chargec | Qg | VDS = 10 V, VGS = 4.5 V, ID =50A | 40 | 40 | Nc |
Gate-Source Chargec | Qgs | 14 | 14 | ||
Gate-Drain Chargec | Qgd | 13 | 13 | ||
Turn-On Delay Timec | td(on) | VDD = 10V, RL = 0.20 ID50A, VGEN = 10 V, RG = 2.5 |
31 | 20 | Ns |
Rise Timec | tr | 18 | 20 | ||
Turn-Off Delay Timec | td(off) | 34 | 50 | ||
Fall Timec | tf | 31 | 15 |
The attached spice model of SUD50N02-04P describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUD50N02-04P is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network of SUD50N02-04P is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUD50N02-04P.